Design Verification Engineer

We are currently partnered with a leading Semiconductor Designer and Manufacturer, who are looking for an experienced Verification Engineer to join their team.

Job Summary:

• Be a key team member in Verification in both IP as Top level verification phases.
• Have a critical focus on reuse and decomposition of the Verification challenges
• Define the Verification Test Specification based on IP/SoC requirements and drive to efficiently closing the Verification Gap within timing and budget constraints.
• Hands-on contributor to IP & SOC verification from scratch, using state-of-art verification methodologies like formal and UVM.
• Setup, deployment and maintenance of the full verification environment to the Verification Team will be your main responsibility.
• Ensure high design quality that meets the stringent demands in the market.
• Reference: MfdtaDewPFh8w356x-h8U-8RIhDgfkCWkFpxWbApxfFbDeA8L4kxEelrXqgZ0fh-

Skills required:

• Knowledge and experience within the Semiconductor industry.
• 5+ years of experience with Verification.
• Experience with C Programming.
• Knowledge of VHDL, Verilog and / or UVM

If this is of interest or you'd like some more information, please get in touch with me.