HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, developed and verified using Cadence tools and flow, and component (VITAL) models for major SoC product developers.
Founded in 2001 and currently employing 170 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS).
For more information, please visit www.hdl-dh.com
Junior Verification Engineer
The ideal candidate will have following skills and background:
- M. Sc. EE or equivalent degree in Electronics, Informatics, Computer Science, Automatic, Telecommunications or Electrical engineering.
- Highly motivated and dynamic engineer able to adopt new technology quickly.
- Familiar with C/C++ and computer architecture.
Additional skills that would be a plus are:
- Familiar with scripting tools and languages (e.g. bash, csh, awk, Perl).
- Familiar with software/hardware development tools (e.g. make and versioning tools (e.g. CVS/SVN).
- Knowledge of C/C++ language and/or SystemC.
- Familiar with complex flows for System-on-Chip projects.
Your key responsibilities would be:
- Involvement in all stages of complex SoC verification including specification, test-bench design, verification plan, development, verification execution and verification sign off.
- Proactive collaboration with team members in different locations
- Review of the verification environment architecture and implementation specifications.
- For all junior engineers there will be 4-6 months technical training. It will be organized in HDL DH premises, executed by senior engineer with teaching experience from the Faculty of Electrical Engineering. The training will be organized based on Cadence (Incisive/X-Celium, Genus, Innovus, Tempus) and Mentor (QuestaSim) EDA tools. During the training period, the junior engineers will not have other assignments and they will have fully paid salary.
- Possibility of working from HDL DH Thessaloniki chip design center for a certain period of time
- Unique chance to join a rapidly expanding company offering fantastic career and skills development opportunities, as well as an exceptional salary
- Permanent employment, private health insurance and additional benefits
- Opportunity to be part of many sports and team building activities with colleagues
- Opportunity to travel abroad and work on our clients’ cites
- Working in young and enthusiastic team
Successful training completion and testing will be condition for candidates to join larger team working in all stages of complex SoC design and verification.
For all candidates proficient knowledge of UNIX/Linux and fluent English is a prerequisite!
Deadline for applications: 15.06.2019.