Senior Digital Design Verification Engineer

Workforce has partnered with the international design house Veriest. Their clients are world's leading chip manufacturers, as well as innovative startups in the field of developing the latest technologies. Areas covered by Veriest projects are: Neural Networks, AI, Data Protection, Automotive (ISO 26262), Networking / Wireless Protocols, Audio / Video Processing, Industrial and Consumer Electronics Applications. We are looking for motivated candidates who will join their expansion at positions: Senior Digital Design Verification Engineer 

Responsibilities:

• Verification plan preparation
• Building verification environments and verification components
• Verification Methodology implementation
• VIPs development
• Perform Failure Analysis and suggest corrective actions
• Development of coverage models
• Architecture design and micro architecture chips
• Design of individual IP blocks, if the whole chip
• ASIC / IP design verification
• Functional verification at all levels: block, cluster and whole chip
• RTL programming in VHDL and Verilog and System verilog
• IP integration and FPGA verification
• Reference: y4SvYBSulhNGmTUS8DQb3ORoADSMQ_HoSU0N9rlaaAM.

Requirements:

• BSc. in electronics /computer engineering / computer science
• 5+years of experience in verification and digital electronics
• IP/SoC design verification experience using System Verilog (UVM) or Specman (e)
• Experience with simulation environments and debug
• Intermediate knowledge of English language
• Knowledge of Verilog / VHDL is a plus
• Knowledge of object-oriented programming is a plus

Profile:

• Motivated and supportive team-player
• Strong written and verbal communication skill
• Problem solving and organisation skill

Some of Benefits: Health insurance, Social Activities, Sports Activities.

Only shortlisted candidates will be contacted.